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71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
LCD38
LCD39
LCD40
LCD41
RTM0
RTM1
RTM2
RTM3
2056
2057
2058
2059
2060
2061
2062
2063
RTM Probes:
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
Synchronous Serial Interface:
RESERVED
RESERVED
RESERVED
RESERVED
SSI
2070
SSI_EN
SSI_10M
SSI_CKGATE
SSI_FSIZE[1:0]
SSI_FPOL
SSI_RDYEN
SSI_RDYPOL
S S I _ B E G 2071
SSI_BEG[7:0]
SSI_END
2072
SSI_END[7:0]
Fuse Selection Registers:
TRIMSEL 20FD
TRIMSEL[7:0]
TRIM
20FF
TRIM[7:0]
SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers.
Name
SFR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Digital I/O:
P0
DIR0
P1
DIR1
P2
DIR2
80
A2
90
91
A0
A1
DIO_0[7:4] (Port 0)
DIO_DIR0[7:4]
DIO_1[7:6] (Port 1)
DIO_DIR1[7:6]
RESERVED
1111
RESERVED
1111
DIO_1[3:0] (Port 1)
DIO_DIR1[3:0]
DIO_2[1:0] (Port 2)
DIO_DIR2[1:0]
Interrupts and WD Timer:
INTBITS
F8
INT6
INT5
INT4
INT3
INT2
INT1
INT0
WDI
E8
WD_RST
IE_RTC
IE_XFER
Flash:
ERASE
94
FLSH_ERASE[7:0]
FLSHCTL
B2
PREBOOT
SECURE
FLSH_MEEN
FLSH_PWE
PGADR
B7
9E
9F
FLSH_PGADR[6:0]
Serial EEPROM:
EEDATA[7:0]
EECTRL[7:0]
Page: 58 of 98
? 2005–2010 Teridian Semiconductor Corporation
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